TSMC to Continue Using Micro-bump Packaging for HBM, Targets 5μm Solution

TSMC plans to maintain the use of traditional micro-bump technology for connecting High Bandwidth Memory (HBM) to AI accelerators in the near term, rather than transitioning to hybrid bonding. According to industry sources, this approach will likely persist through the late stages of HBM4 and the early stages of HBM5. TSMC has requested that material and equipment partners develop bonding and underfill solutions for 5μm-level bumps, with mass production expected to begin in the second half of 2028. Current HBM3E bumps measure approximately 15–25μm, while HB